Semiconductor devices can include input/output (I/O) drivers at interface connections. There exists an increasing demand for I/O drivers which can tolerate high drain and gate voltages without incurring hot carrier or gate oxide degradation. The scaling of gate oxides in deep sub-micron technologies in combination with customer demands for mixed voltage product applications has forced designers to create I/O drivers which meet such demands.
One method to achieve both lower hot carrier generation and reduce the maximum field across the gate oxide is to use cascode configured output drivers. Conventional cascoded I/O drivers typically include plural MOS devices intermediate the I/O pad and power and/or ground.
It is generally recognized that some semiconductor devices are susceptible to damage from electrical overstress conditions (EOS). These conditions occur when the voltage or amperage ratings for a circuit are exceeded. Exemplary electrical overstress conditions include electrostatic discharge (ESD), transient conditions, latch-up, incorrect polarity connections, etc. The electrical overstress conditions are characterized by over-voltage and over-current stress events.
Overcoming electrostatic discharge conditions continues to increase in importance as the sensitivity of semiconductor devices increases. Electrostatic charge (ESC) can accumulate in a body and damage semiconductor devices and circuitry therein if the body is brought into contact with the devices. For example, a person may accumulate electrostatic charge by walking across carpeting. The accumulated electrostatic charge can be imparted to semiconductor devices touched by the individual. Some semiconductor devices are sufficiently sensitive that the resultant flow of charge imparted to the device results in permanent damage to the semiconductor device.
Accordingly, it is highly desired to protect semiconductor devices from electrostatic discharge and other electrical overstress conditions. Some solutions have attempted to minimize the accumulation of electrostatic charge to prevent electrostatic discharge. Exemplary solutions have included utilization of protective clothing such as shoes, smocks, etc. for workers in the semiconductor industry. Such approaches may alleviate the problem of electrostatic discharge to some extent but consumers may not be aware of the potential damaging effects of electrostatic discharge upon the electronic components being handled.
Other approaches for abating electrical overstress conditions and electrostatic discharge events with regard to electrical components has included providing electrostatic discharge components within the electrical or semiconductor components themselves. Conventional methods of implementing electrostatic discharge current protection for semiconductor devices include providing discharge paths in parallel to I/O pads of the semiconductor device being protected.
Such methods can be successful at alleviating susceptibility to electrostatic discharge damage, but also introduce other drawbacks. For example, the electrostatic discharge protection devices can increase capacitance at the I/O pads resulting in decreased performance of the semiconductor device. Decreased performance is highly undesirable inasmuch as speed of some semiconductor devices is of paramount importance. Another exemplary drawback includes the consumption of additional surface area of the substrate to implement the electrical overstress and electrostatic discharge protection.
Therefore, there exists a need to provide improved protection from electrical overstress conditions which overcomes the drawbacks associated with the prior art.